1. Field of the Invention
The present invention relates to an insulated gate field effect transistor (hereinafter referred to as a MIS-FET).
2. Description of the Prior Art
Recently, attention has been given to a power MIS-FET. The power MIS-FET has characteristics such that no thermal runaway appears becaus of negative temperature coefficient of drain current, input impedance is high, switching can be performed at high speed and enhancement mode is easily obtainable.
A double diffused vertical-type construction has been applied for the power MIS-FET. In this construction, the drain region is formed by a semiconductor substrate so that current density per unit area can be easily increased.
A shown in FIG. 1, the double diffused vertical-type MIS-FET is formed of an N-type semiconductor substrate 1 serving as a drain region, a P-type base region or a channel forming region 2 which is formed by a selective diffusion process and faced to one major surface 1a o the semiconductor substrate 1, and an N-type source region 3 which is selectively formed on the base region 2 by, for example, a selective diffusion process. Then, a V-shaped groove 5 is formed by etching or the like from the major surface 1a side of the substrate 1 penetrating through the source region 3 and the base region 2. The V-shaped groove 5 has deposited therein a gate insulating layer 6 on which is deposited a gate electrode 7. Meanwhile, facing the other major surface 1b of the substrate 1 serving as the drain region 4 there is provided a high concentration region 4A from which a drain terminal D is led out. Reference numeral 8 designates a source electrode deposited extending over the source region 3 and base region 2, and S and G indicate a source terminal and a gate terminal.
In the MIS-FET as described above, a channel 9 is formed in the base region 2 at its portion in contact with the gate insulating layer 6 deposited in the etched groove 5. In this case, the channel length, that is, the distance between the source and drain regions 3 and 4 with the channel 9 interposed therebetween is defined by the difference between the diffused depths of the base region 2 and source region 3. Therefore, a quite small channel length can be obtained by properly selecting the diffused depths of the regions 2 and 3.
In the MIS-FET having such a construction, however, there are drawbacks such that the process for forming the groove 5 is quite troublesome and also it is difficult to reproduce MIS-FETs with uniform characteristics.